Cheers for all the additional detail and care to explain the situation!
My only other question would be—it seems the natural way to continue the scaling trend would be to learn to stack more and more transistors on top of each other, until a chip becomes a fully 3D object. I understand that the main obstacle at the moment is preventing them from overheating but I’ve no idea how soluble it is.
Do you have a good understanding or reference for the feasibility of this direction?
I understand that the main obstacle at the moment is preventing them from overheating but I’ve no idea how soluble it is.
That’s a serious theoretical concern way down the line; it’s nowhere near the most pressing concern.
The enemy is # of wafer passes necessary, and knock-on effects thereof. If your machine does a million wafer passes a year, it can produce 100k chips a year requiring 10 wafer passes each… or 1 chip requiring 1m wafer passes. (And meanwhile, if each pass has a 1% chance of causing a critical failure, your yield rate is ~90% in the former case, and 10−4363% or so in the latter case.)
No-one has figured out how to do n vertical layers of transistors in sub-O(n) passes. The closest thing to that is 3D NAND, but even there it’s still O(n) passes. (There are some theoretical approaches to getting sublinear mask steps with 3d nand, but it still generally requires O(n) other steps.)
(And 3D nand is very much a best-case in a bunch of ways. It’s extremely regular compared to the transistors in the middle of e.g. an ALU, for instance. And doesn’t mind the penalty for running in a 40nm process. Etc.)
(And even 3D NAND is hitting scaling limitations. “String stacking” is essentially a tact acknowledgement that you can’t move beyond ~128 layers or so, so ‘just’ put multiple stacks on top of each other on the chip… but this is again O(n) passes / layer on average, just with a lower constant.)
As long as making multiple transistor layers is O(n) passes and time/pass is roughly a plateau, moving to multiple levels doesn’t actually help scaling, and meanwhile hurts yield.
Cheers for all the additional detail and care to explain the situation!
My only other question would be—it seems the natural way to continue the scaling trend would be to learn to stack more and more transistors on top of each other, until a chip becomes a fully 3D object. I understand that the main obstacle at the moment is preventing them from overheating but I’ve no idea how soluble it is.
Do you have a good understanding or reference for the feasibility of this direction?
That’s a serious theoretical concern way down the line; it’s nowhere near the most pressing concern.
The enemy is # of wafer passes necessary, and knock-on effects thereof. If your machine does a million wafer passes a year, it can produce 100k chips a year requiring 10 wafer passes each… or 1 chip requiring 1m wafer passes. (And meanwhile, if each pass has a 1% chance of causing a critical failure, your yield rate is ~90% in the former case, and 10−4363% or so in the latter case.)
No-one has figured out how to do n vertical layers of transistors in sub-O(n) passes. The closest thing to that is 3D NAND, but even there it’s still O(n) passes. (There are some theoretical approaches to getting sublinear mask steps with 3d nand, but it still generally requires O(n) other steps.)
(Relevant: https://thememoryguy.com/making-3d-nand-flash-animated-video/ , and his series on 3d nand in general ( https://thememoryguy.com/what-is-3d-nand-why-do-we-need-it-how-do-they-make-it/ ). )
(And 3D nand is very much a best-case in a bunch of ways. It’s extremely regular compared to the transistors in the middle of e.g. an ALU, for instance. And doesn’t mind the penalty for running in a 40nm process. Etc.)
(And even 3D NAND is hitting scaling limitations. “String stacking” is essentially a tact acknowledgement that you can’t move beyond ~128 layers or so, so ‘just’ put multiple stacks on top of each other on the chip… but this is again O(n) passes / layer on average, just with a lower constant.)
As long as making multiple transistor layers is O(n) passes and time/pass is roughly a plateau, moving to multiple levels doesn’t actually help scaling, and meanwhile hurts yield.