Minor nit, your assertion of C=ϵ0L is too simple imo, even for a Fermi estimate. At the very least, include a factor of 4 for the dielectric constant of SiO2, and iirc in real interconnects there is a relatively high “minimum” from fringing fields. I can try to find a source for that later tonight, but I would expect it ends up significantly more than 10×ϵ0. This will actually make your estimate agree even better with Jacob’s.
This page suggests that people have stopped using SiO2 as the “interlayer dielectric” in favor of (slightly) lower-dielectric constant materials, and also that Intel has a process for using air gaps for at least some of the interconnect layers, I think?
Looking at images like this, yeah there do seem to be lots of pretty narrow gaps.
I am very open-minded to editing the central estimate of what is feasible. It sounds like you know more about this topic than me.
No you’re right, use 2 or 3 instead of 4 as an average dielectric constant. The document you linked cites https://ieeexplore.ieee.org/abstract/document/7325600 which gives measured resistances and capacitances for the various layers. For Intel’s 14 nm process making use of low-k, ultra-low-k dielectrics, and air gaps, they show numbers down to 0.15 fF/micron, about 15 times higher than ϵ0.
I remember learning that aspect ratio and dielectric constant alone don’t suffice to explain the high capacitances of interconnects. Instead, you have to include fringe fields—turns out they’re not actually infinite parallel plates (gasp!).
Again, it’s not a big deal and doesn’t detract much from your analysis. I somewhat regret even bringing it up because of how not important it is :)
This is an excellent writeup.
Minor nit, your assertion of C=ϵ0L is too simple imo, even for a Fermi estimate. At the very least, include a factor of 4 for the dielectric constant of SiO2, and iirc in real interconnects there is a relatively high “minimum” from fringing fields. I can try to find a source for that later tonight, but I would expect it ends up significantly more than 10×ϵ0. This will actually make your estimate agree even better with Jacob’s.
This page suggests that people have stopped using SiO2 as the “interlayer dielectric” in favor of (slightly) lower-dielectric constant materials, and also that Intel has a process for using air gaps for at least some of the interconnect layers, I think?
Looking at images like this, yeah there do seem to be lots of pretty narrow gaps.
I am very open-minded to editing the central estimate of what is feasible. It sounds like you know more about this topic than me.
No you’re right, use 2 or 3 instead of 4 as an average dielectric constant. The document you linked cites https://ieeexplore.ieee.org/abstract/document/7325600 which gives measured resistances and capacitances for the various layers. For Intel’s 14 nm process making use of low-k, ultra-low-k dielectrics, and air gaps, they show numbers down to 0.15 fF/micron, about 15 times higher than ϵ0.
I remember learning that aspect ratio and dielectric constant alone don’t suffice to explain the high capacitances of interconnects. Instead, you have to include fringe fields—turns out they’re not actually infinite parallel plates (gasp!).
Again, it’s not a big deal and doesn’t detract much from your analysis. I somewhat regret even bringing it up because of how not important it is :)
I just edited the text, thanks.