Just made this account to answer this. Source: I’ve worked in physical design/VLSI and CPU verification, and pretty regularly deal with RTL.
TL;DR—You’re right—it’s not a big deal, but it simultaneously means more and less than you think.
The Problem
Jump to “What It Means” if you already understand the problem.
First, let me talk about about the purpose of floorplanning. The author’s mention it a little bit, but it’s worth repeating.
Placement optimizations of this form appear in a wide range of science and engineering applications, including hardware design, city planning, vaccine testing and distribution, and cerebral cortex layout.
Much like a city, an SoC (system-on-chip) has lots of agents that transfer data to each other. If a mayor has to get to city hall, the library, the post office, the locksmith, the school, the burger joint, etc., how do you best place the buildings to get the shortest path to each of them? Suppose suddenly the librarian wants to first go to school, then the post office, and also a burger because they have 20% off. How do you position that requirement along with the mayor’s requirement? Do you prioritize the mayor? What if he wants a burger too? What if it’s not guaranteed the number of paths the mayor will take before returning to city hall Etc. etc.
As you probably know, placement in general is an NP-complete problem. Tools for this exist, and/or you can do it manually, but much like city planning, it gets very complicated very fast. These tools (if you wanna sound cool, call them PnR tools (place-and-route)) take foooreeever to run (it’s quite common to let a tool run for a week) and are critical in the holistic design lifecycle—more on that later.
Enter this paper. Honestly, they don’t do any revolutionary stuff—CNNs, ReLu, weight adjustment—or rather, it’s revolutionary because it’s applied to PnR for the first time that I’ve seen at least (which, in hindsight, is pretty obvious. Pulling up the GUI for the tool, it’s literally just a grid, exactly like a city, with its own centers and everything. Still cool nevertheless).
Let’s talk about results!
I don’t know how to do tables in comments, so bear with the formatting—here are the results for one test they did:
Note: I left out “Congestion” and “wire length” because those are metrics that tbh don’t really matter
Method
Timing
Total area (µm 2 )
Total power (W)
(wns)
(tns)
RePlAce
374
233.7
1,693,139
3.70
Manual
136
47.6
1,680,790
3.74
Our method
84
23.3
1,681,767
3.59
Don’t worry what wns and tns exactly mean (here are a few resources). Just know that they are essentially a measure of how short a “path” is between “buildings”. The smaller it is, the better, because it means our mayor can travel less distance to get his burger.
Area and power are relatively explanatory—essentially, how big is your city + all the roads you’ve built, and how much energy does it take to run it all. Again, the smaller the better.
What It Means
These are good results! We’ve just built roads that are twice as short vs. our manual methods! (23.3 vs. 47.6). But, I want to provide my opinion for why it’s even worse than you think (i.e., I don’t even think it would provide a 1% increase in perf, much in the same way that increasing CPU GHz doesn’t do that much—it’s inherently limited), but also much better
For why it’s worse—consider again city planning. Suppose we take this to the extreme and the burger joint, library, post office, etc are all literally inside the same building as City Hall (i.e. no roads exist). First, his arteries will certainly get clogged passing by a McDonalds, but ultimately—How much performance/time saved does the mayor really save?
I would argue that, while it depends on how convoluted the city was initially, there’s a limit to how much you can shrink the roads and place the buildings. While these planning efforts are very much important to strive for, it’s not the real bottleneck.
Furthermore, what if this travel time was time simultaneously being well-spent already? For instance—perhaps he checked his emails walking to the post office. Maybe he called his mother. Maybe he brought his meeting notes to practice a speech. The point is—this travel time is not really saved: just reallocated.
Note: CPUs do this a lot, e.g. while a memory request is occurring, they just switch to do some other tasks. This is also (to vastly oversimplify) essentially why frequency scaling no longer had immense payoffs as it did 30 years ago.
Now that I’ve killed your enthusiasm, let me tell you why it’s also better than you think with this quote.
We show that our method can generate chip floorplans that are comparable or superior to human experts in under six hours, whereas humans take months to produce acceptable floorplans for modern accelerators
I mentioned earlier that designers heavily rely on PnR tools not only prior to tapeout, but as tools to iterate over (e.g. can I mux this more efficiently? Do I really need this logic in the critical path? Can this “building” be shifted over? etc.) As these tools take longer as our designs become more complex, it ultimately results in a longer feedback loop—again, a week sometimes—and personally, I really like instant gratification, so it’s definitely a bit annoying.
And this is why it’s potentially better—it’s indicative of a step towards freeing up resources of what I feel is a massive cost to many semiconductor companies. Not just for better and tighter feedback loops, but because these PnR/physical design/EDA tool teams are massive. Like, hundreds of people sometimes. And these people ultimately have the final signoff for lots of tapeouts, and determine timelines for hardware companies.
Go 5 years in the future, and give them a tool that improves engineer productivity 100x? Honestly, that’d be insane. For me personally, but also for my colleagues. (Honestly, not sure what I’d do with that extra time. I currently just cook stuff while I’m blocked- :) )
So, that’s why I think it’s both better and worse than you think.
Awesome, thanks! And welcome to LW! I found this very helpful and now have some follow-up questions if you don’t mind. :)
1. How does this square with Zac’s answer below? It on the surface seems to contradict what you say; after all, it proposes 10x-1000x improvements to AI stuff whereas you say it won’t even be 1%! I think I can see a way that your two answers can be interpreted as consistent, however: You identify the main benefit of this tech as reducing the clock time it takes for engineers to come up with a new good chip design. So even if the new design is only 1% better than the design the engineers would have come up with, if it happens a lot faster, that’s a big deal. Why is it a big deal? Well, as Zac said, it means the latest AI architectures can be quickly supplemented by custom chips, and in general custom chips provide 10x − 1000x speedups. Would you agree with this synthesis?
2. I’d be interested in your best guess for what the median X’s and Y’s in this sentence are: “In about X years, we’ll be in a regime where the latest AI models are run on specialized hardware that provides a factor-of-Y speedup over today’s hardware.”
3. ETA: Maybe another big implication of this technology is that it’ll lower the barrier to entry for new chipmakers? Like, maybe 5 years from now there’ll be off-the-shelf AI techniques that let people design cutting-edge new chips, and so China and Russia and India and everyone will have their own budding chip industry supported by generous government subsidies. Or maybe not—maybe most of the barriers to entry have to do with manufacturing talent rather than design talent?
I thought I wrote an answer to this. Turns out I didn’t. Also, I am a horrific procrastinator.
In some sense, I’d agree with this synthesis. I say some sense, because the other bottleneck that lots of chip designs have is verification. Somebody has to test the new crazy shit a designer might create, right? To go back to our city planner analogy—sure, perhaps you create the most optimal connections between buildings. But what if the designer but the doors on the roof, because it’s the fastest way down? Yes, designs can be come up with faster, and can theoretically be fabbed out faster. But, as with anything that depends on humans, that itself 1) has a certain amount of complexity that builds technical debt and 2) requires inspection. To me, this is like how software engineering has A) the actual development and B) the deployment to production. No matter how fast B) is, which may certainly aid in iteration, A) is still heavily gated by humans.
It’s hard to give a concrete answer for that, since there are A) so many different AI models and B) so many different hardware architectures to run those AI models. AI is a full-stack problem, that honestly still has lots of room to grow, so any advance in any component of the stack will produce growth. Put a gun to my head though—x = 3, y = 2
Though not in this specific paper/iteration, this technology definitely has potential to lower time-to-fab—more specifically, post-silicon fabrication. But, you see, I don’t think the barrier to entry is post-silicon fabrication. It is creating the design in the first place, and verifying it. This is what ARM does—they already provide pre-verified designs (reference implementations) for you to rip off of and, as is, ship out. Just give them licensing fees! Furthermore, in many ways, a 1-2 year lead time is kinda built in already in our society (think of it—you usually buy new hardware every couple years, right?). Thus, suppose you completely eliminate post-silicon fabrication times. Where would this extra time go? I highly doubt we would change our society-accepted cadence of hardware rotations. Most definitely, it would go right back into creating new designs—human brains. Thus, I think the biggest barrier to entry is knowledge and engineering talent. Manufacturing talent is, frankly, thanks to TSMC’s duopoly in foundries, not much of a barrier. Sure, it’s a barrier that China is tackling (see the whole SMIC fiasco) but not one much of the Western world is willing to tackle. So, again, that just circles back to design talent.
All in all, I rebuff my original point that this isn’t that big of a deal, but is still insanely cool. I’d love to heavily advance this technology, because it’s pretty god damn annoying, but it just means I’d have more time to sit on my hands, and that’s no guarantee I’d do anything good with that time!
Thanks! As before, this was helpful & I have some follow-up questions. :) Feel free to not reply if you don’t want to.
1. Can verification be automated too, in the next 10 years?
2. Quantitatively, about how much time + money does a good version of this automated chip design save? E.g. “It normally takes 1 year to design a chip and 2 years to actually scale up production; this tech turns that 1 year into 1 month (when you include verification), for an overall time savings of 33%. As for cost, design is a small fraction of the cost (even a research team of hundreds for a year is nothing compared to the cost of a manufacturing line or whatever) so the effect is negligible.”
3. y = 2? That’s way lower y than I expected, especially considering that you “rebuff my original point that this isn’t that big of a deal.” A 2x improvement in 3 years is NOT a big deal, right? Isn’t that slightly slower than the historical rate of progress from e.g. moore’s law etc.? Or are you saying it’s going to be a 2x improvement on top of the regular progress from other sources? Oh… maybe you are specifically talking about speed improvements rather than all-things-considered cost to train a model of a given size on a given dataset? It’s the latter that I’m interested in, I probably misspoke.
4. What is post-silicon fabrication? When I google it it redirects to “post-silicon validation.” If creating the design and verifying it is the barrier to entry, then won’t this AI tech help reduce the barrier to entry since it automates the design part? I guess I just don’t understand your point 3.
5. “Thus, suppose you completely eliminate post-silicon fabrication times. Where would this extra time go? I highly doubt we would change our society-accepted cadence of hardware rotations. Most definitely, it would go right back into creating new designs—human brains. ” I’m particularly keen to hear what you mean by this.
Definitely not in the next 10 years. In some sense, that’s what formal verification is all about. There’s progress, but from my perspective, it’s a very linear growth. The tools that I have seen (e.g. out of the RISC-V Summit, or DVCon) are difficult to adopt, and there’s a large inertia you have to overcome since many big Semi companies already have their own custom flows built up over decades. I think it’ll take a young plucky startup to adopt and push for the usage of these tools—but even then, you need the talent to learn these tools, and frankly hardware is filled with old people.
I think we have different interpretations of “design”. You consider chip design in the aggregate, but I’m subdividing it into multiple areas. There’s several aspects of chip design, some of which can be automated, but I’m claiming never to an extreme extent as e.g. 1 month. This technology in particular really only helps in determining where to place “buildings” but not really much in actually building the “buildings” themselves. While valuable, there’s only so much “placing” can do. My view is that, the time and money spent won’t go down, just reallocated, which may or may not increase quality.
Sorry, I guess I meant the former where I incorporate every source, at least on the hardware side. Were you to isolate just the ML Chip placement gain… again, hard to say. It’s just indicative of a release of resources, but who knows if those extra resources can/will be properly directed to something better?
+ 5. : Sorry! I guess I meant post-design fabrication, which is really just a term I came up with to mean “shipping it to TSMC once you’re done designing”. A better term, in hindsight, is just called “tapeout”, but I was hesitant to use the term time-to-tapeout since that feels cumulative rather than isolating that one period of time I mean.
What I mean is that, this technology is addressing the “Physical Design” blob of time as above. Notice that the whole critical path to “Shipping”/getting the chips out there goes “Verification”--> “Tapeout” --> “Validation”/Testing
Suppose the “Physical Design” time gets eliminated. These freed resources will most definitely go into “RTL Design” and not “Verification”. That’s what I mean by “creating new designs”—it gives us more time to think of cool stuff, but again, depends if that stuff is good or not.
Why will extra resources not be devoted to verification? That’s a whole can of worms. Industry inertia, overlapping talent skillset, business models, design complexity—but I guess most of all I’d say inertia.
On inertia—as I said, this cadence takes about 1-2 years. We are so so so very accustomed to this cadence, I can’t see it changing barring massive changes in our needs. If you told me you could reduce our verification time from 1 year to 11 months, I’d just spend that extra month iterating on my RTL design instead, or use that extra time to run more simulations, because 11 vs. 12 months doesn’t mean much.
If you told me I could reduce it from 1 year --> 6 months? I’d maaaaybe throw money at you. It has potential to double my income, but that depends.
Imagine new iPhones came out every 6 months instead of yearly. Isn’t that super weird? Well… That depends on how well Apple can market to me that I absolutely need it.
Perhaps that differs for AI use cases… but even there, I’d argue this yearly cadence is ingrained already
Just made this account to answer this. Source: I’ve worked in physical design/VLSI and CPU verification, and pretty regularly deal with RTL.
TL;DR—You’re right—it’s not a big deal, but it simultaneously means more and less than you think.
The Problem
Jump to “What It Means” if you already understand the problem.
First, let me talk about about the purpose of floorplanning. The author’s mention it a little bit, but it’s worth repeating.
Much like a city, an SoC (system-on-chip) has lots of agents that transfer data to each other. If a mayor has to get to city hall, the library, the post office, the locksmith, the school, the burger joint, etc., how do you best place the buildings to get the shortest path to each of them? Suppose suddenly the librarian wants to first go to school, then the post office, and also a burger because they have 20% off. How do you position that requirement along with the mayor’s requirement? Do you prioritize the mayor? What if he wants a burger too? What if it’s not guaranteed the number of paths the mayor will take before returning to city hall Etc. etc.
As you probably know, placement in general is an NP-complete problem. Tools for this exist, and/or you can do it manually, but much like city planning, it gets very complicated very fast. These tools (if you wanna sound cool, call them PnR tools (place-and-route)) take foooreeever to run (it’s quite common to let a tool run for a week) and are critical in the holistic design lifecycle—more on that later.
Enter this paper. Honestly, they don’t do any revolutionary stuff—CNNs, ReLu, weight adjustment—or rather, it’s revolutionary because it’s applied to PnR for the first time that I’ve seen at least (which, in hindsight, is pretty obvious. Pulling up the GUI for the tool, it’s literally just a grid, exactly like a city, with its own centers and everything. Still cool nevertheless).
Let’s talk about results!
I don’t know how to do tables in comments, so bear with the formatting—here are the results for one test they did:
Note: I left out “Congestion” and “wire length” because those are metrics that tbh don’t really matter
Don’t worry what wns and tns exactly mean (here are a few resources). Just know that they are essentially a measure of how short a “path” is between “buildings”. The smaller it is, the better, because it means our mayor can travel less distance to get his burger.
Area and power are relatively explanatory—essentially, how big is your city + all the roads you’ve built, and how much energy does it take to run it all. Again, the smaller the better.
What It Means
These are good results! We’ve just built roads that are twice as short vs. our manual methods! (23.3 vs. 47.6). But, I want to provide my opinion for why it’s even worse than you think (i.e., I don’t even think it would provide a 1% increase in perf, much in the same way that increasing CPU GHz doesn’t do that much—it’s inherently limited), but also much better
For why it’s worse—consider again city planning. Suppose we take this to the extreme and the burger joint, library, post office, etc are all literally inside the same building as City Hall (i.e. no roads exist). First, his arteries will certainly get clogged passing by a McDonalds, but ultimately—How much performance/time saved does the mayor really save?
I would argue that, while it depends on how convoluted the city was initially, there’s a limit to how much you can shrink the roads and place the buildings. While these planning efforts are very much important to strive for, it’s not the real bottleneck.
Furthermore, what if this travel time was time simultaneously being well-spent already? For instance—perhaps he checked his emails walking to the post office. Maybe he called his mother. Maybe he brought his meeting notes to practice a speech. The point is—this travel time is not really saved: just reallocated.
Note: CPUs do this a lot, e.g. while a memory request is occurring, they just switch to do some other tasks. This is also (to vastly oversimplify) essentially why frequency scaling no longer had immense payoffs as it did 30 years ago.
Now that I’ve killed your enthusiasm, let me tell you why it’s also better than you think with this quote.
I mentioned earlier that designers heavily rely on PnR tools not only prior to tapeout, but as tools to iterate over (e.g. can I mux this more efficiently? Do I really need this logic in the critical path? Can this “building” be shifted over? etc.) As these tools take longer as our designs become more complex, it ultimately results in a longer feedback loop—again, a week sometimes—and personally, I really like instant gratification, so it’s definitely a bit annoying.
And this is why it’s potentially better—it’s indicative of a step towards freeing up resources of what I feel is a massive cost to many semiconductor companies. Not just for better and tighter feedback loops, but because these PnR/physical design/EDA tool teams are massive. Like, hundreds of people sometimes. And these people ultimately have the final signoff for lots of tapeouts, and determine timelines for hardware companies.
Go 5 years in the future, and give them a tool that improves engineer productivity 100x? Honestly, that’d be insane. For me personally, but also for my colleagues. (Honestly, not sure what I’d do with that extra time. I currently just cook stuff while I’m blocked- :) )
So, that’s why I think it’s both better and worse than you think.
Mod here, I put a table in your comment.
(Tables aren’t in comment editors right now, I made it in the post editor and copied it in.)
This is a great comment! Thank you for writing it!
Awesome, thanks! And welcome to LW! I found this very helpful and now have some follow-up questions if you don’t mind. :)
1. How does this square with Zac’s answer below? It on the surface seems to contradict what you say; after all, it proposes 10x-1000x improvements to AI stuff whereas you say it won’t even be 1%! I think I can see a way that your two answers can be interpreted as consistent, however: You identify the main benefit of this tech as reducing the clock time it takes for engineers to come up with a new good chip design. So even if the new design is only 1% better than the design the engineers would have come up with, if it happens a lot faster, that’s a big deal. Why is it a big deal? Well, as Zac said, it means the latest AI architectures can be quickly supplemented by custom chips, and in general custom chips provide 10x − 1000x speedups. Would you agree with this synthesis?
2. I’d be interested in your best guess for what the median X’s and Y’s in this sentence are: “In about X years, we’ll be in a regime where the latest AI models are run on specialized hardware that provides a factor-of-Y speedup over today’s hardware.”
3. ETA: Maybe another big implication of this technology is that it’ll lower the barrier to entry for new chipmakers? Like, maybe 5 years from now there’ll be off-the-shelf AI techniques that let people design cutting-edge new chips, and so China and Russia and India and everyone will have their own budding chip industry supported by generous government subsidies. Or maybe not—maybe most of the barriers to entry have to do with manufacturing talent rather than design talent?
I thought I wrote an answer to this. Turns out I didn’t. Also, I am a horrific procrastinator.
In some sense, I’d agree with this synthesis.
I say some sense, because the other bottleneck that lots of chip designs have is verification. Somebody has to test the new crazy shit a designer might create, right? To go back to our city planner analogy—sure, perhaps you create the most optimal connections between buildings. But what if the designer but the doors on the roof, because it’s the fastest way down?
Yes, designs can be come up with faster, and can theoretically be fabbed out faster. But, as with anything that depends on humans, that itself 1) has a certain amount of complexity that builds technical debt and 2) requires inspection.
To me, this is like how software engineering has A) the actual development and B) the deployment to production. No matter how fast B) is, which may certainly aid in iteration, A) is still heavily gated by humans.
It’s hard to give a concrete answer for that, since there are A) so many different AI models and B) so many different hardware architectures to run those AI models. AI is a full-stack problem, that honestly still has lots of room to grow, so any advance in any component of the stack will produce growth.
Put a gun to my head though—x = 3, y = 2
Though not in this specific paper/iteration, this technology definitely has potential to lower time-to-fab—more specifically, post-silicon fabrication.
But, you see, I don’t think the barrier to entry is post-silicon fabrication. It is creating the design in the first place, and verifying it. This is what ARM does—they already provide pre-verified designs (reference implementations) for you to rip off of and, as is, ship out. Just give them licensing fees!
Furthermore, in many ways, a 1-2 year lead time is kinda built in already in our society (think of it—you usually buy new hardware every couple years, right?). Thus, suppose you completely eliminate post-silicon fabrication times. Where would this extra time go? I highly doubt we would change our society-accepted cadence of hardware rotations. Most definitely, it would go right back into creating new designs—human brains. Thus, I think the biggest barrier to entry is knowledge and engineering talent.
Manufacturing talent is, frankly, thanks to TSMC’s duopoly in foundries, not much of a barrier. Sure, it’s a barrier that China is tackling (see the whole SMIC fiasco) but not one much of the Western world is willing to tackle.
So, again, that just circles back to design talent.
All in all, I rebuff my original point that this isn’t that big of a deal, but is still insanely cool. I’d love to heavily advance this technology, because it’s pretty god damn annoying, but it just means I’d have more time to sit on my hands, and that’s no guarantee I’d do anything good with that time!
Thanks! As before, this was helpful & I have some follow-up questions. :) Feel free to not reply if you don’t want to.
1. Can verification be automated too, in the next 10 years?
2. Quantitatively, about how much time + money does a good version of this automated chip design save? E.g. “It normally takes 1 year to design a chip and 2 years to actually scale up production; this tech turns that 1 year into 1 month (when you include verification), for an overall time savings of 33%. As for cost, design is a small fraction of the cost (even a research team of hundreds for a year is nothing compared to the cost of a manufacturing line or whatever) so the effect is negligible.”
3. y = 2? That’s way lower y than I expected, especially considering that you “rebuff my original point that this isn’t that big of a deal.” A 2x improvement in 3 years is NOT a big deal, right? Isn’t that slightly slower than the historical rate of progress from e.g. moore’s law etc.? Or are you saying it’s going to be a 2x improvement on top of the regular progress from other sources? Oh… maybe you are specifically talking about speed improvements rather than all-things-considered cost to train a model of a given size on a given dataset? It’s the latter that I’m interested in, I probably misspoke.
4. What is post-silicon fabrication? When I google it it redirects to “post-silicon validation.” If creating the design and verifying it is the barrier to entry, then won’t this AI tech help reduce the barrier to entry since it automates the design part? I guess I just don’t understand your point 3.
5. “Thus, suppose you completely eliminate post-silicon fabrication times. Where would this extra time go? I highly doubt we would change our society-accepted cadence of hardware rotations. Most definitely, it would go right back into creating new designs—human brains. ” I’m particularly keen to hear what you mean by this.
Definitely not in the next 10 years. In some sense, that’s what formal verification is all about. There’s progress, but from my perspective, it’s a very linear growth.
The tools that I have seen (e.g. out of the RISC-V Summit, or DVCon) are difficult to adopt, and there’s a large inertia you have to overcome since many big Semi companies already have their own custom flows built up over decades.
I think it’ll take a young plucky startup to adopt and push for the usage of these tools—but even then, you need the talent to learn these tools, and frankly hardware is filled with old people.
I think we have different interpretations of “design”. You consider chip design in the aggregate, but I’m subdividing it into multiple areas. There’s several aspects of chip design, some of which can be automated, but I’m claiming never to an extreme extent as e.g. 1 month. This technology in particular really only helps in determining where to place “buildings” but not really much in actually building the “buildings” themselves. While valuable, there’s only so much “placing” can do.
My view is that, the time and money spent won’t go down, just reallocated, which may or may not increase quality.
Sorry, I guess I meant the former where I incorporate every source, at least on the hardware side. Were you to isolate just the ML Chip placement gain… again, hard to say. It’s just indicative of a release of resources, but who knows if those extra resources can/will be properly directed to something better?
+ 5. : Sorry! I guess I meant post-design fabrication, which is really just a term I came up with to mean “shipping it to TSMC once you’re done designing”. A better term, in hindsight, is just called “tapeout”, but I was hesitant to use the term time-to-tapeout since that feels cumulative rather than isolating that one period of time I mean.
See: https://anysilicon.com/verification-validation-testing-asic-soc-designs-differences/
What I mean is that, this technology is addressing the “Physical Design” blob of time as above. Notice that the whole critical path to “Shipping”/getting the chips out there goes “Verification”--> “Tapeout” --> “Validation”/Testing
Suppose the “Physical Design” time gets eliminated. These freed resources will most definitely go into “RTL Design” and not “Verification”. That’s what I mean by “creating new designs”—it gives us more time to think of cool stuff, but again, depends if that stuff is good or not.
Why will extra resources not be devoted to verification? That’s a whole can of worms. Industry inertia, overlapping talent skillset, business models, design complexity—but I guess most of all I’d say inertia.
On inertia—as I said, this cadence takes about 1-2 years. We are so so so very accustomed to this cadence, I can’t see it changing barring massive changes in our needs. If you told me you could reduce our verification time from 1 year to 11 months, I’d just spend that extra month iterating on my RTL design instead, or use that extra time to run more simulations, because 11 vs. 12 months doesn’t mean much.
If you told me I could reduce it from 1 year --> 6 months? I’d maaaaybe throw money at you. It has potential to double my income, but that depends.
Imagine new iPhones came out every 6 months instead of yearly. Isn’t that super weird? Well… That depends on how well Apple can market to me that I absolutely need it.
Perhaps that differs for AI use cases… but even there, I’d argue this yearly cadence is ingrained already