where the bottleneck is outside the part being improved.
I work in CAD, and I can assure you that the users of my department’s code are very interested in performance improvements. The CAD software run time is a major bottleneck in designing the next generation of computers.
I work in CAD, and I can assure you that the users of my department’s code are very interested in performance improvements.
Might I suggest that the greatest improvements in CAD performance will come from R&D into CAD techniques and software? At least, that seems to be the case basically everywhere else. Not to belittle computing power but the software to use the raw power tends to be far more critical. If this wasn’t the case, and given that much of the CAD task can be parellelized, recursive self improvement in computer chip self improvement would result in an exponentially expanding number of exponentially improving supercomputer clusters. On the scale of “We’re using 30% of the chips we create to make new supercomputers instead of selling them. We’ll keep doing that until our processors are sufficiently ahead of ASUS that we can reinvest less of our production capacity and still be improving faster than all competitors”.
I think folk like yourself and the researchers into CAD are the greater bottleneck here. That’s a compliment to the importance of your work. I think. Or maybe an insult to your human frailty. I never can tell. :)
Jed Harris says similar things in the comments here, but this seems to make predictions that don’t seem born out to me (cf wedrifid). If serial runtime is a recursive bottleneck, then the break of exponentially increasing clockspeed should cause problems for the chip design process and then also break exponential transistor density. But if these processes can be parallelized, then they should have been parallelized long ago.
A way to reconcile some of these claims is that serial clockspeed has only recently become a bottleneck, as a result of the clockspeed plateau.
I work in CAD, and I can assure you that the users of my department’s code are very interested in performance improvements. The CAD software run time is a major bottleneck in designing the next generation of computers.
Might I suggest that the greatest improvements in CAD performance will come from R&D into CAD techniques and software? At least, that seems to be the case basically everywhere else. Not to belittle computing power but the software to use the raw power tends to be far more critical. If this wasn’t the case, and given that much of the CAD task can be parellelized, recursive self improvement in computer chip self improvement would result in an exponentially expanding number of exponentially improving supercomputer clusters. On the scale of “We’re using 30% of the chips we create to make new supercomputers instead of selling them. We’ll keep doing that until our processors are sufficiently ahead of ASUS that we can reinvest less of our production capacity and still be improving faster than all competitors”.
I think folk like yourself and the researchers into CAD are the greater bottleneck here. That’s a compliment to the importance of your work. I think. Or maybe an insult to your human frailty. I never can tell. :)
Jed Harris says similar things in the comments here, but this seems to make predictions that don’t seem born out to me (cf wedrifid). If serial runtime is a recursive bottleneck, then the break of exponentially increasing clockspeed should cause problems for the chip design process and then also break exponential transistor density. But if these processes can be parallelized, then they should have been parallelized long ago.
A way to reconcile some of these claims is that serial clockspeed has only recently become a bottleneck, as a result of the clockspeed plateau.