You are missing the point. There are hyper-dimensional topological solutions that can be efficiently implement on vanilla silicon that obviate your argument. There is literature to support the conjecture even if there is not literature to support the implementation. Nonetheless, implementations are known to have recently been developed at places like IBM Research that have been publicly disclosed to exist (if not the design). (ObDisclosure: I developed much of the practical theory related to this domain—I’ve seen running code at scale). Just because the brain exists in three dimensions does not imply that it is a 3-dimensional data model any more than analogous things are implied on a computer.
It is not an abstraction, you can implement these directly on silicon. There are very old theorems that allow the implementation of hyper-dimensional topological constructs on vanilla silicon (since the 1960s), conjectured to support massive pervasive parallelism (since the 1940s), the reduction to practice just isn’t obvious and no one is taught these things. These models scale well on mediocre switch fabrics if competently designed.
Basically, you are extrapolating a “we can’t build algorithms on switch fabrics” bias improperly and without realizing you are doing it. State-of-the-art parallel computer science research is much more interesting than you are assuming. Ironically, the mathematics behind it is completely indifferent to dimensionality.
You are missing the point. There are hyper-dimensional topological solutions that can be efficiently implement on vanilla silicon that obviate your argument. There is literature to support the conjecture even if there is not literature to support the implementation.
I’m totally missing how a “hyper-dimension topological solution” could get around the physical limitation of being realized on a 2D printed circuit. I guess if you use enough layers?
Do you have a link to an example paper about this?
It is analogous to how you can implement a hyper-cube topology on a physical network in normal 3-space, which is trivial. Doing it virtually on a switch fabric is trickier.
Hyper-dimensionality is largely a human abstraction when talking about algorithms; a set of bits can be interpreted as being in however many dimensions is convenient for an algorithm at a particular point in time, which follows from fairly boring maths e.g. Morton’s theorems. The general concept of topological computation is not remarkable either, it has been around since Tarski, it just is not obvious how one reduces it to useful practice.
There is no literature on what a reduction to practice would even look like but it is a bit of an open secret in the world of large-scale graph analysis that the very recent ability of a couple companies to parallelize graph analysis are based on something like this. Graph analysis scalability is closely tied to join algorithm scalability—a well-known hard-to-parallelize operation.
You are missing the point. There are hyper-dimensional topological solutions that can be efficiently implement on vanilla silicon that obviate your argument. There is literature to support the conjecture even if there is not literature to support the implementation. Nonetheless, implementations are known to have recently been developed at places like IBM Research that have been publicly disclosed to exist (if not the design). (ObDisclosure: I developed much of the practical theory related to this domain—I’ve seen running code at scale). Just because the brain exists in three dimensions does not imply that it is a 3-dimensional data model any more than analogous things are implied on a computer.
It is not an abstraction, you can implement these directly on silicon. There are very old theorems that allow the implementation of hyper-dimensional topological constructs on vanilla silicon (since the 1960s), conjectured to support massive pervasive parallelism (since the 1940s), the reduction to practice just isn’t obvious and no one is taught these things. These models scale well on mediocre switch fabrics if competently designed.
Basically, you are extrapolating a “we can’t build algorithms on switch fabrics” bias improperly and without realizing you are doing it. State-of-the-art parallel computer science research is much more interesting than you are assuming. Ironically, the mathematics behind it is completely indifferent to dimensionality.
I’m totally missing how a “hyper-dimension topological solution” could get around the physical limitation of being realized on a 2D printed circuit. I guess if you use enough layers?
Do you have a link to an example paper about this?
It is analogous to how you can implement a hyper-cube topology on a physical network in normal 3-space, which is trivial. Doing it virtually on a switch fabric is trickier.
Hyper-dimensionality is largely a human abstraction when talking about algorithms; a set of bits can be interpreted as being in however many dimensions is convenient for an algorithm at a particular point in time, which follows from fairly boring maths e.g. Morton’s theorems. The general concept of topological computation is not remarkable either, it has been around since Tarski, it just is not obvious how one reduces it to useful practice.
There is no literature on what a reduction to practice would even look like but it is a bit of an open secret in the world of large-scale graph analysis that the very recent ability of a couple companies to parallelize graph analysis are based on something like this. Graph analysis scalability is closely tied to join algorithm scalability—a well-known hard-to-parallelize operation.